Regviz

NXP Semiconductors /MKL26Z4 /NVIC /NVIC_ISER

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as NVIC_ISER

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/MKL26Z4/NVIC/NVIC_ISER#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SETENA0 0 (0)SETENA1 0 (0)SETENA2 0 (0)SETENA3 0 (0)SETENA4 0 (0)SETENA5 0 (0)SETENA6 0 (0)SETENA7 0 (0)SETENA8 0 (0)SETENA9 0 (0)SETENA10 0 (0)SETENA11 0 (0)SETENA12 0 (0)SETENA13 0 (0)SETENA14 0 (0)SETENA15 0 (0)SETENA16 0 (0)SETENA17 0 (0)SETENA18 0 (0)SETENA19 0 (0)SETENA20 0 (0)SETENA21 0 (0)SETENA22 0 (0)SETENA23 0 (0)SETENA24 0 (0)SETENA25 0 (0)SETENA26 0 (0)SETENA27 0 (0)SETENA28 0 (0)SETENA29 0 (0)SETENA30 0 (0)SETENA31

SETENA28=0, SETENA3=0, SETENA26=0, SETENA2=0, SETENA20=0, SETENA12=0, SETENA29=0, SETENA31=0, SETENA30=0, SETENA11=0, SETENA10=0, SETENA14=0, SETENA9=0, SETENA8=0, SETENA13=0, SETENA16=0, SETENA19=0, SETENA25=0, SETENA7=0, SETENA22=0, SETENA27=0, SETENA23=0, SETENA21=0, SETENA18=0, SETENA6=0, SETENA17=0, SETENA1=0, SETENA24=0, SETENA15=0, SETENA0=0, SETENA4=0, SETENA5=0

Description

Interrupt Set Enable Register

Fields

SETENA0

DMA channel 0 transfer complete and error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 0 transfer complete and error interrupt disabled

1 (1): write: enable DMA channel 0 transfer complete and error interrupt; read: DMA channel 0 transfer complete and error interrupt enabled
SETENA1

DMA channel 1 transfer complete and error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 1 transfer complete and error interrupt disabled

1 (1): write: enable DMA channel 1 transfer complete and error interrupt; read: DMA channel 1 transfer complete and error interrupt enabled
SETENA2

DMA channel 2 transfer complete and error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 2 transfer complete and error interrupt disabled

1 (1): write: enable DMA channel 2 transfer complete and error interrupt; read: DMA channel 2 transfer complete and error interrupt enabled
SETENA3

DMA channel 3 transfer complete and error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 3 transfer complete and error interrupt disabled

1 (1): write: enable DMA channel 3 transfer complete and error interrupt; read: DMA channel 3 transfer complete and error interrupt enabled
SETENA4

Reserved iv 20 interrupt set-enable bit

0 (0): write: no effect; read: Reserved iv 20 interrupt disabled

1 (1): write: enable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
SETENA5

FTFA command complete and read collision interrupt set-enable bit

0 (0): write: no effect; read: FTFA command complete and read collision interrupt disabled

1 (1): write: enable FTFA command complete and read collision interrupt; read: FTFA command complete and read collision interrupt enabled
SETENA6

low-voltage detect and low-voltage warning interrupt set-enable bit

0 (0): write: no effect; read: low-voltage detect and low-voltage warning interrupt disabled

1 (1): write: enable low-voltage detect and low-voltage warning interrupt; read: low-voltage detect and low-voltage warning interrupt enabled
SETENA7

low leakage wakeup interrupt set-enable bit

0 (0): write: no effect; read: low leakage wakeup interrupt disabled

1 (1): write: enable low leakage wakeup interrupt; read: low leakage wakeup interrupt enabled
SETENA8

inter-integrated circuit 0 interrupt set-enable bit

0 (0): write: no effect; read: inter-integrated circuit 0 interrupt disabled

1 (1): write: enable inter-integrated circuit 0 interrupt; read: inter-integrated circuit 0 interrupt enabled
SETENA9

inter-integrated circuit 1 interrupt set-enable bit

0 (0): write: no effect; read: inter-integrated circuit 1 interrupt disabled

1 (1): write: enable inter-integrated circuit 1 interrupt; read: inter-integrated circuit 1 interrupt enabled
SETENA10

serial peripheral interface 0 interrupt set-enable bit

0 (0): write: no effect; read: serial peripheral interface 0 interrupt disabled

1 (1): write: enable serial peripheral interface 0 interrupt; read: serial peripheral interface 0 interrupt enabled
SETENA11

serial peripheral interface 1 interrupt set-enable bit

0 (0): write: no effect; read: serial peripheral interface 1 interrupt disabled

1 (1): write: enable serial peripheral interface 1 interrupt; read: serial peripheral interface 1 interrupt enabled
SETENA12

UART0 status and error interrupt set-enable bit

0 (0): write: no effect; read: UART0 status and error interrupt disabled

1 (1): write: enable UART0 status and error interrupt; read: UART0 status and error interrupt enabled
SETENA13

UART1 status and error interrupt set-enable bit

0 (0): write: no effect; read: UART1 status and error interrupt disabled

1 (1): write: enable UART1 status and error interrupt; read: UART1 status and error interrupt enabled
SETENA14

UART2 status and error interrupt set-enable bit

0 (0): write: no effect; read: UART2 status and error interrupt disabled

1 (1): write: enable UART2 status and error interrupt; read: UART2 status and error interrupt enabled
SETENA15

Analog-to-digital converter 0 interrupt set-enable bit

0 (0): write: no effect; read: Analog-to-digital converter 0 interrupt disabled

1 (1): write: enable Analog-to-digital converter 0 interrupt; read: Analog-to-digital converter 0 interrupt enabled
SETENA16

Comparator 0 interrupt set-enable bit

0 (0): write: no effect; read: Comparator 0 interrupt disabled

1 (1): write: enable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
SETENA17

Timer PWM module 0 interrupt set-enable bit

0 (0): write: no effect; read: Timer PWM module 0 interrupt disabled

1 (1): write: enable Timer PWM module 0 interrupt; read: Timer PWM module 0 interrupt enabled
SETENA18

Timer PWM module 1 interrupt set-enable bit

0 (0): write: no effect; read: Timer PWM module 1 interrupt disabled

1 (1): write: enable Timer PWM module 1 interrupt; read: Timer PWM module 1 interrupt enabled
SETENA19

Timer PWM module 2 interrupt set-enable bit

0 (0): write: no effect; read: Timer PWM module 2 interrupt disabled

1 (1): write: enable Timer PWM module 2 interrupt; read: Timer PWM module 2 interrupt enabled
SETENA20

real time clock alarm interrupt set-enable bit

0 (0): write: no effect; read: real time clock alarm interrupt disabled

1 (1): write: enable real time clock alarm interrupt; read: real time clock alarm interrupt enabled
SETENA21

real time clock seconds interrupt set-enable bit

0 (0): write: no effect; read: real time clock seconds interrupt disabled

1 (1): write: enable real time clock seconds interrupt; read: real time clock seconds interrupt enabled
SETENA22

periodic interrupt timer all channels interrupt set-enable bit

0 (0): write: no effect; read: periodic interrupt timer all channels interrupt disabled

1 (1): write: enable periodic interrupt timer all channels interrupt; read: periodic interrupt timer all channels interrupt enabled
SETENA23

integrated interchip sound 0 interrupt set-enable bit

0 (0): write: no effect; read: integrated interchip sound 0 interrupt disabled

1 (1): write: enable integrated interchip sound 0 interrupt; read: integrated interchip sound 0 interrupt enabled
SETENA24

universal serial bus on the go interrupt set-enable bit

0 (0): write: no effect; read: universal serial bus on the go interrupt disabled

1 (1): write: enable universal serial bus on the go interrupt; read: universal serial bus on the go interrupt enabled
SETENA25

digital-to-analog converter 0 interrupt set-enable bit

0 (0): write: no effect; read: digital-to-analog converter 0 interrupt disabled

1 (1): write: enable digital-to-analog converter 0 interrupt; read: digital-to-analog converter 0 interrupt enabled
SETENA26

touch sensing input interrupt set-enable bit

0 (0): write: no effect; read: touch sensing input interrupt disabled

1 (1): write: enable touch sensing input interrupt; read: touch sensing input interrupt enabled
SETENA27

multipurpose clock generator interrupt set-enable bit

0 (0): write: no effect; read: multipurpose clock generator interrupt disabled

1 (1): write: enable multipurpose clock generator interrupt; read: multipurpose clock generator interrupt enabled
SETENA28

Low-Power Timer interrupt set-enable bit

0 (0): write: no effect; read: Low-Power Timer interrupt disabled

1 (1): write: enable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
SETENA29

Reserved iv 45 interrupt set-enable bit

0 (0): write: no effect; read: Reserved iv 45 interrupt disabled

1 (1): write: enable Reserved iv 45 interrupt; read: Reserved iv 45 interrupt enabled
SETENA30

PORTA pin detect interrupt set-enable bit

0 (0): write: no effect; read: PORTA pin detect interrupt disabled

1 (1): write: enable PORTA pin detect interrupt; read: PORTA pin detect interrupt enabled
SETENA31

PORTC and PORTD pin detect interrupt set-enable bit

0 (0): write: no effect; read: PORTC and PORTD pin detect interrupt disabled

1 (1): write: enable PORTC and PORTD pin detect interrupt; read: PORTC and PORTD pin detect interrupt enabled

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data